1. Technical Field
The present invention relates generally to the field of semiconductor fabrication. In particular, the present invention discloses a system and method for designing one or more grating structures for use in situ scatterometry to provide early warning of pattern integrity defects during the fabrication process.
2. Description of the Related Art
The semiconductor industry is constantly striving to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. The semiconductor industry is fueled by developer and consumer demand for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. Thus, there is a constant drive to reduce the size of the components of a typical transistor in order to increase the overall speed of the transistor.
An exemplary field effect transistor 10 is shown in FIG. 1. The transistor 10 generally includes the following components: a wafer body 12, a surface of the wafer body 12A, a gate electrode 14, a gate insulator 16, a source 18, a drain 20, and isolation regions 22. The wafer body 12 is typically comprised of appropriately doped Silicon (Si), Gallium Arsenide (GaAs) or Geranium (Ge). By way of example, common dopants for Silicon include Phosphorous (P) and Arsenic (As) as N-type transistors and Boron (B) for P-type transistors. In the process of forming integrated circuit devices, millions of transistors are formed on the surface of the wafer body 12A. The wafer body 12 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The source 18 and the drain 20 elements of the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms into the wafer body 12. Isolation regions 22 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors located within the wafer body 12 (not shown).
In addition, although not shown in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, commonly referred to as conductive lines or vias, positioned in multiple layers of insulating material formed above the wafer body 12. These conductive interconnections allow electrical signals to propagate between the transistors formed above the wafer body 12.
Due to the complexity and the microscopic size of these transistors, there are many dimensions that are critical for the fabrication process, e.g., the width of the gate electrode 14, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, metals, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are repeated until such time as the integrated circuit device is complete.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. Due to the complexity and reduced size of these devices, it is very important that these features be formed as accurately as possible. For example, the width of the gate electrode 14 corresponds approximately to the channel length 24 of the transistor 10 when it is operational. Accordingly, even slight variations in the actual dimension of this feature as fabricated may adversely affect device performance. Thus, there is a great need for a system and method that may be used to accurately, reliably and repeatedly troubleshoot and form features to their desired critical dimension.
Photolithography is a process commonly employed in semiconductor manufacturing. Photolithography generally involves forming a layer of photoresist material (positive or negative) above one or more layers of material, e.g., polysilicon, silicon dioxide, that are desired to be patterned. Thereafter, a pattern that is desired to be formed in the underlying layer or layers of material is initially formed in the layer of photoresist using an appropriate stepper or scanning tool and known photolithographic techniques, i.e., an image on a reticle in the stepper tool is transferred to the layer of photoresist. The layer of photoresist is then developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
In one exemplary embodiment, modern photolithography processes generally involve the steps of: (1) applying a layer of photoresist above a wafer, typically accomplished by a spin-coating process; (2) pre-baking (or soft-baking) the layer of photoresist at a temperature of approximately 90-120 degree Celsius to reduce the level of solvents in the layer of photoresist and to improve the adhesion characteristics of the photoresist; (3) performing an exposure process, wherein a pattern is projected onto the layer of photoresist through a reticle used in a stepper tool to create a latent image in the layer of photoresist; (4) performing a post-exposure bake on the layer of photoresist at a temperature approximately 5-15 degree Celsius higher than the pre-bake process; (5) performing a develop process to turn the latent image in the layer of photoresist into the final resist image; and (6) performing a post-bake process (or hard-bake) at a temperature of approximately 125-160 degree Celsius to remove residual solids, improve adhesion, and to increase the etch resistance of the photoresist.
Due the pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged, there is a corresponding need to increase the resolution capability of photolithography systems. To accomplish this goal, relatively short wavelengths (e.g., less than about 258 nm) have been used for the illumination light source. In conjunction with these relatively short wavelengths, ultra thin resists (UTR) have been used. For example, many applications include the use of photo resist layers that have a thickness of about 0.1 micron or thinner.
Further background for the present invention will now be described with reference to FIGS. 2 and 3. As shown in FIG. 2, a process layer 26 is formed above a wafer body 12 (or other previously-formed process layer) and a layer of photoresist material 28 (positive or negative) is formed above the process layer 26. The process layer 26 is meant to be illustrative of any type of material that may be patterned using known photolithographic and etching techniques. Using known photolithographic techniques, the layer of photoresist material 28 is patterned to define a plurality of photoresist features 28A that are intended to be used as a mask in patterning the underlying process layer 26 as illustrated in FIG. 3. This mask may also be referred to herein as a patterned photoresist mask.
For a variety of reasons, the photolithography process described above may result in imperfect semiconductor fabrication. Common problems associated with semiconductor fabrication are photoresist erosion, photoresist bending and pattern collapse. As semiconductors continue to shrink, the photolithography requirements become much more demanding. A consequence of this is photoresists that are thinner and inherently less resistant to erosion by the etching process. Likewise, photoresist bending and the collapse of photolithographic patterns occur during the etch process when a rinse solution, usually water, is removed from the surface in a spin drying step. As the water is removed, capillary forces, caused by the surface tension of water between densely packed photoresist features, cause the pattern to bend and in some instances to ultimately collapse. In general, capillary forces increase as the separation between photoresist features decreases. Since the minimum distance between lithographic features has been predicted to decrease from 180 nm in 1999 to 100 nm in 2009, the bending and collapse of photoresist features is expected to have a significant impact on the next generation of semiconductors.
Photoresist erosion, photoresist bending and pattern collapse during plasma etch may result in significant defects in the semiconductor and possibly result in the scrapping of the underlying wafer bodies. It is desirable to detect such photoresist problems early in the photolithography process before they require scrapping of the underlying wafer bodies.
The cause of many of the problems mentioned above arises directly from the photolithography process. For example, photolithography processes using 248 nm exposure tools can be used to develop photoresist patterned masks with critical dimensions typically down to 180 nm at best. Advanced exposure tools and photoresist formulas are required to routinely achieve critical dimensions of 150 nm or less. However, logic applications often require smaller gate width dimensions, necessitating further trimming of the developed photoresist before the photoresist pattern is transferred to the underlying film. This process is typically referred to as trim etch (also referred to as plasma etch). As shown in FIG. 4, the resist line 30 on substrate 31 has a width denoted by DICD. The width of resist line 30 is wider than the desired gate to be formed, as illustrated by the dashed line. For example, a typical deep-UV stepper in certain embodiments provides reliable resolution capabilities down to 0.25 μm. To provide for gate width that is less than 0.25 μm, the 0.25 μm wide photoresist line is isotropically etched in a controlled manner in a high-density plasma etching system, to provide etching in horizontal directions A1, A2 along with etching in the vertical direction B, until a narrower final line, having a final critical dimension (FICD), remains.
Since a photoresist line with a relatively large DICD requires a relatively long trim etch time to achieve a given FICD, a significant amount of the photoresist is normally etched away in a vertical direction B, resulting in a substantial weakening and thinning of the photoresist 30. This significant reduction of the vertical dimension or thickness of the photoresist 30 from its untrimmed vertical dimension can promote discontinuity thereof, resulting in the photoresist 30 being incapable of providing effective masking in the fabrication of the gate. As in the case of a relatively small DICD, a photoresist with a small vertical photoresist dimension is required in order to prevent pattern collapse and/or bending caused by the capillary forces (discussed above), due to an undesirably high aspect ratio (“AR”), i.e., height/width ratio, of the partially etched resist structure.
Thus, there is a strong need in the art for a system and method to provide early warning of photoresist pattern integrity during photoresist pattern development thereby preventing or substantially reducing the need to scrap wafer bodies.